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<!@TC:1540516105>
#Build: Synplify Pro (R) N-2018.03G-Beta6, Build 118R, May 15 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 8 6.2
#Hostname: BEACONDEV3

# Fri Oct 26 09:08:25 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport1></a>Synopsys HDL Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1540516106> | Running in 64-bit mode 

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport2></a>Synopsys Verilog Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1540516106> | Running in 64-bit mode 
@N: : <!@TM:1540516106> | : Running Verilog Compiler in System Verilog mode 
@N: : <!@TM:1540516106> | : Running Verilog Compiler in Multiple File Compilation Unit mode 
@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\fpga_led_tm1637\src\spi_master.v" (library work)
@I::"C:\fpga_led_tm1637\src\led_tm1637.v" (library work)
@I:"C:\fpga_led_tm1637\src\led_tm1637.v":"C:\fpga_led_tm1637\src\rom.v" (library work)
@I::"C:\fpga_led_tm1637\src\led_tm1637_rom.v" (library work)
Verilog syntax check successful!
Selecting top level module demo
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637_rom.v:3:7:3:21:@N:CG364:@XP_MSG">led_tm1637_rom.v(3)</a><!@TM:1540516106> | Synthesizing module LED_TM1637_ROM in library work.
Opening data file led_tm1637_rom.mem from directory C:\fpga_led_tm1637\src
<font color=#A52A2A>@W:<a href="@W:CG532:@XP_HELP">CG532</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637_rom.v:12:0:12:7:@W:CG532:@XP_MSG">led_tm1637_rom.v(12)</a><!@TM:1540516106> | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\fpga_led_tm1637\src\spi_master.v:3:7:3:17:@N:CG364:@XP_MSG">spi_master.v(3)</a><!@TM:1540516106> | Synthesizing module spi_master in library work.

	DIO_MODE=32'b00000000000000000000000000000001
	CLOCK_MODE=32'b00000000000000000000000000000011
	LSB_FIRST=32'b00000000000000000000000000000001
	WORD_LEN=32'b00000000000000000000000000001000
	PRESCALER_SIZE=32'b00000000000000000000000000001000
	PRESCALER=32'b00000000000000000000000000000000
	STATE_IDLE=1'b0
	STATE_BUSY=1'b1
   Generated name = spi_master_1s_3s_1s_8s_8s_0s_0_1
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:5:7:5:11:@N:CG364:@XP_MSG">led_tm1637.v(5)</a><!@TM:1540516106> | Synthesizing module demo in library work.
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL169:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Pruning unused register test_display_on[7:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL169:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Pruning unused register test_display_off[7:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL207:@XP_HELP">CL207</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL207:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | All reachable assignments to tm1637_vcc assign 1, register removed by optimization.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL190:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Optimizing register bit repeat_count[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL260:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Pruning register bit 14 of repeat_count[14:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL190:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Optimizing register bit repeat_count[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL260:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Pruning register bit 13 of repeat_count[13:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL190:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Optimizing register bit repeat_count[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL260:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Pruning register bit 12 of repeat_count[12:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL190:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Optimizing register bit repeat_count[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:CL260:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516106> | Pruning register bit 11 of repeat_count[11:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 86MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Oct 26 09:08:26 2018

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport3></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1540516106> | Running in 64-bit mode 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:5:7:5:11:@N:NF107:@XP_MSG">led_tm1637.v(5)</a><!@TM:1540516106> | Selected library: work cell: demo view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:5:7:5:11:@N:NF107:@XP_MSG">led_tm1637.v(5)</a><!@TM:1540516106> | Selected library: work cell: demo view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Oct 26 09:08:26 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Oct 26 09:08:26 2018

###########################################################]

</pre></samp></body></html>
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<!@TC:1540516105>

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Database state : C:\fpga_led_tm1637\impl\synthesize\rev_1\synwork\|rev_1
<a name=compilerReport4></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1540516108> | Running in 64-bit mode 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:5:7:5:11:@N:NF107:@XP_MSG">led_tm1637.v(5)</a><!@TM:1540516108> | Selected library: work cell: demo view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\fpga_led_tm1637\src\led_tm1637.v:5:7:5:11:@N:NF107:@XP_MSG">led_tm1637.v(5)</a><!@TM:1540516108> | Selected library: work cell: demo view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Oct 26 09:08:28 2018

###########################################################]

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<!@TC:1540516105>
Premap Report


</pre></samp></body></html>
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<!@TC:1540516105>
# Fri Oct 26 09:08:28 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport5></a>Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1540516111> | No constraint file specified. 
Linked File:  <a href="C:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637_scck.rpt:@XP_FILE">fpga_led_tm1637_scck.rpt</a>
Printing clock  summary report in "C:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637_scck.rpt" file 
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1540516111> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1540516111> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1540516111> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1540516111> | UMR3 is only supported for HAPS-80. 
@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1540516111> | UMR3 is only supported for HAPS-80. 
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:BN362:@XP_MSG">spi_master.v(179)</a><!@TM:1540516111> | Removing sequential instance ss (in view: work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N:<a href="@N:MF578:@XP_HELP">MF578</a> : <!@TM:1540516111> | Incompatible asynchronous control logic preventing generated clock conversion. 
syn_allowed_resources : blockrams=10  set on top level netlist demo

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)



<a name=mapperReport6></a>Clock Summary</a>
******************

          Start                                Requested     Requested     Clock                                         Clock                     Clock
Level     Clock                                Frequency     Period        Type                                          Group                     Load 
--------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       demo|clk_50M                         100.0 MHz     10.000        inferred                                      Autoconstr_clkgroup_0     26   
1 .         demo|clk_spi_derived_clock         100.0 MHz     10.000        derived (from demo|clk_50M)                   Autoconstr_clkgroup_0     144  
2 ..          demo|wr_spi_derived_clock[0]     100.0 MHz     10.000        derived (from demo|clk_spi_derived_clock)     Autoconstr_clkgroup_0     10   
2 ..          demo|rd_spi_derived_clock[0]     100.0 MHz     10.000        derived (from demo|clk_spi_derived_clock)     Autoconstr_clkgroup_0     1    
========================================================================================================================================================



Clock Load Summary
***********************

                                 Clock     Source                    Clock Pin                         Non-clock Pin     Non-clock Pin
Clock                            Load      Pin                       Seq Example                       Seq Example       Comb Example 
--------------------------------------------------------------------------------------------------------------------------------------
demo|clk_50M                     26        clk_50M(port)             clk_spi.C                         -                 -            
demo|clk_spi_derived_clock       144       clk_spi.Q[0](dffre)       rd_spi[0].C                       -                 -            
demo|wr_spi_derived_clock[0]     10        wr_spi[0].Q[0](dffre)     spi0._tx_buffer_occupied[0].C     -                 -            
demo|rd_spi_derived_clock[0]     1         rd_spi[0].Q[0](dffre)     spi0._rx_buffer_received[0].C     -                 -            
======================================================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:38:0:38:6:@W:MT529:@XP_MSG">led_tm1637.v(38)</a><!@TM:1540516111> | Found inferred clock demo|clk_50M which controls 26 sequential elements including cnt[24:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



<a name=clockReport7></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

1 non-gated/non-generated clock tree(s) driving 26 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 155 clock pin(s) of sequential element(s)
0 instances converted, 155 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
<a href="@|L:C:\fpga_led_tm1637\impl\synthesize\rev_1\synwork\fpga_led_tm1637_prem.srm@|S:clk_50M@|E:cnt[24:0]@|F:@syn_dgcc_clockid0_7==1@|M:ClockId_0_7 @XP_NAMES_BY_PROP">ClockId_0_7</a>       clk_50M             Unconstrained_port     26         cnt[24:0]      
=======================================================================================
=================================================================== Gated/Generated Clocks ===================================================================
Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance                 Explanation                               
--------------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|L:C:\fpga_led_tm1637\impl\synthesize\rev_1\synwork\fpga_led_tm1637_prem.srm@|S:clk_spi.Q[0]@|E:step_id[6:0]@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1 @XP_NAMES_BY_PROP">ClockId_0_1</a>       clk_spi.Q[0]        dffre                  144                    step_id[6:0]                    Derived clock on input (not legal for GCC)
<a href="@|L:C:\fpga_led_tm1637\impl\synthesize\rev_1\synwork\fpga_led_tm1637_prem.srm@|S:wr_spi[0].Q[0]@|E:spi0._tx_buffer[7:0]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3 @XP_NAMES_BY_PROP">ClockId_0_3</a>       wr_spi[0].Q[0]      dffre                  10                     spi0._tx_buffer[7:0]            Derived clock on input (not legal for GCC)
<a href="@|L:C:\fpga_led_tm1637\impl\synthesize\rev_1\synwork\fpga_led_tm1637_prem.srm@|S:rd_spi[0].Q[0]@|E:spi0._rx_buffer_received[0]@|F:@syn_dgcc_clockid0_5==1@|M:ClockId_0_5 @XP_NAMES_BY_PROP">ClockId_0_5</a>       rd_spi[0].Q[0]      dffre                  1                      spi0._rx_buffer_received[0]     Derived clock on input (not legal for GCC)
==============================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: : <!@TM:1540516111> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1540516111> | Writing default property annotation file C:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 190MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 190MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 190MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Oct 26 09:08:31 2018

###########################################################]

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<!@TC:1540516105>
Map & Optimize Report


</pre></samp></body></html>
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<!@TC:1540516105>
# Fri Oct 26 09:08:31 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport8></a>Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1540516117> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1540516117> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1540516117> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1540516117> | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 190MB)

@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:MO231:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Found counter in view:work.demo(verilog) instance repeat_count[10:0] 
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:BN362:@XP_MSG">spi_master.v(179)</a><!@TM:1540516117> | Removing sequential instance _rx_buffer[4] (in view: work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:BN362:@XP_MSG">spi_master.v(179)</a><!@TM:1540516117> | Removing sequential instance _rx_buffer[5] (in view: work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:BN362:@XP_MSG">spi_master.v(179)</a><!@TM:1540516117> | Removing sequential instance _rx_buffer[6] (in view: work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:BN362:@XP_MSG">spi_master.v(179)</a><!@TM:1540516117> | Removing sequential instance _rx_buffer[7] (in view: work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:BN362:@XP_MSG">spi_master.v(179)</a><!@TM:1540516117> | Removing sequential instance _shift_reg_rx[7] (in view: work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:BN362:@XP_MSG">spi_master.v(179)</a><!@TM:1540516117> | Removing sequential instance _shift_reg_rx[6] (in view: work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:BN362:@XP_MSG">spi_master.v(179)</a><!@TM:1540516117> | Removing sequential instance _shift_reg_rx[5] (in view: work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:BN362:@XP_MSG">spi_master.v(179)</a><!@TM:1540516117> | Removing sequential instance _shift_reg_rx[4] (in view: work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog)) because it does not drive other instances.
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:179:0:179:6:@N:MO231:@XP_MSG">spi_master.v(179)</a><!@TM:1540516117> | Found counter in view:work.spi_master_1s_3s_1s_8s_8s_0s_0_1(verilog) instance _prescaler_cnt[7:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637_rom.v:13:14:13:24:@N:MO106:@XP_MSG">led_tm1637_rom.v(13)</a><!@TM:1540516117> | Found ROM oled_rom_init.dout_1[47:0] (in view: work.demo(verilog)) with 128 words by 48 bits.
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@W:BN132:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing instance tx_data[3] because it is equivalent to instance tx_data[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:66:0:66:6:@W:BN132:@XP_MSG">spi_master.v(66)</a><!@TM:1540516117> | Removing instance spi0._tx_buffer[3] because it is equivalent to instance spi0._tx_buffer[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[0] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[1] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[2] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[3] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[4] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[5] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[6] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[7] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[8] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[9] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[10] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[11] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[12] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[13] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[14] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[15] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[16] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[17] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[18] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[19] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[20] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[21] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[22] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[23] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[24] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[25] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[26] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance saved_elapsed_time[27] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance rd_spi[0] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[0] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[1] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[2] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[3] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[4] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[5] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[6] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[7] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[8] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[9] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\led_tm1637.v:188:0:188:6:@N:BN362:@XP_MSG">led_tm1637.v(188)</a><!@TM:1540516117> | Removing sequential instance repeat_count[10] (in view: work.demo(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_led_tm1637\src\spi_master.v:335:0:335:6:@N:BN362:@XP_MSG">spi_master.v(335)</a><!@TM:1540516117> | Removing sequential instance spi0._rx_buffer_received[0] (in view: work.demo(verilog)) because it does not drive other instances.

Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 197MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		     3.35ns		 262 /       130
   2		0h:00m:01s		     1.31ns		 260 /       130

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 197MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1540516117> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 197MB)

@N:<a href="@N:MT611:@XP_HELP">MT611</a> : <!@TM:1540516117> | Automatically generated clock demo|rd_spi_derived_clock[0] is not used and is being removed 

Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 124MB peak: 197MB)

Writing Analyst data base C:\fpga_led_tm1637\impl\synthesize\rev_1\synwork\fpga_led_tm1637_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 197MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 197MB)

@N:<a href="@N:BW103:@XP_HELP">BW103</a> : <!@TM:1540516117> | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:<a href="@N:BW107:@XP_HELP">BW107</a> : <!@TM:1540516117> | Synopsys Constraint File capacitance units using default value of 1pF  
@A:<a href="@A:BN540:@XP_HELP">BN540</a> : <!@TM:1540516117> | No min timing constraints supplied; adding min timing constraints 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 197MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 197MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1540516117> | Found inferred clock demo|clk_50M with period 10.00ns. Please declare a user-defined clock on port clk_50M.</font> 
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1540516117> | Found clock demo|clk_spi_derived_clock with period 10.00ns  
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1540516117> | Found clock demo|wr_spi_derived_clock[0] with period 10.00ns  


<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
<a name=pnr10></a># Timing Report written on Fri Oct 26 09:08:36 2018</a>
#


Top view:               demo
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1540516117> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1540516117> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary11></a>Performance Summary</a>
*******************


Worst slack in design: -3.887

                                 Requested     Estimated     Requested     Estimated                Clock                                         Clock                
Starting Clock                   Frequency     Frequency     Period        Period        Slack      Type                                          Group                
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
demo|clk_50M                     100.0 MHz     94.6 MHz      10.000        10.568        -0.568     inferred                                      Autoconstr_clkgroup_0
demo|clk_spi_derived_clock       100.0 MHz     105.4 MHz     10.000        9.483         1.033      derived (from demo|clk_50M)                   Autoconstr_clkgroup_0
demo|wr_spi_derived_clock[0]     100.0 MHz     118.6 MHz     10.000        8.434         1.566      derived (from demo|clk_spi_derived_clock)     Autoconstr_clkgroup_0
System                           100.0 MHz     866.6 MHz     10.000        1.154         8.846      system                                        system_clkgroup      
=======================================================================================================================================================================





<a name=clockRelationships12></a>Clock Relationships</a>
*******************

Clocks                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------------------
Starting                      Ending                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------------------
System                        demo|clk_spi_derived_clock    |  10.000      8.846   |  No paths    -      |  No paths    -      |  No paths    -    
System                        demo|wr_spi_derived_clock[0]  |  10.000      8.846   |  No paths    -      |  No paths    -      |  No paths    -    
demo|clk_50M                  demo|clk_50M                  |  10.000      -0.568  |  No paths    -      |  No paths    -      |  No paths    -    
demo|clk_spi_derived_clock    System                        |  10.000      -3.887  |  No paths    -      |  No paths    -      |  No paths    -    
demo|clk_spi_derived_clock    demo|clk_spi_derived_clock    |  10.000      1.033   |  No paths    -      |  No paths    -      |  No paths    -    
demo|clk_spi_derived_clock    demo|wr_spi_derived_clock[0]  |  10.000      5.266   |  No paths    -      |  No paths    -      |  No paths    -    
demo|wr_spi_derived_clock[0]  System                        |  10.000      6.498   |  No paths    -      |  No paths    -      |  No paths    -    
demo|wr_spi_derived_clock[0]  demo|clk_spi_derived_clock    |  10.000      1.566   |  No paths    -      |  No paths    -      |  No paths    -    
demo|wr_spi_derived_clock[0]  demo|wr_spi_derived_clock[0]  |  10.000      15.333  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo13></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport14></a>Detailed Report for Clock: demo|clk_50M</a>
====================================



<a name=startingSlack15></a>Starting Points with Worst Slack</a>
********************************

             Starting                                      Arrival           
Instance     Reference        Type     Pin     Net         Time        Slack 
             Clock                                                           
-----------------------------------------------------------------------------
cnt[1]       demo|clk_50M     DFFC     Q       cnt[1]      0.367       -0.568
cnt[0]       demo|clk_50M     DFFC     Q       cnt[0]      0.367       -0.501
cnt[4]       demo|clk_50M     DFFC     Q       cnt[4]      0.367       -0.291
cnt[8]       demo|clk_50M     DFFC     Q       cnt[8]      0.367       -0.291
cnt[7]       demo|clk_50M     DFFC     Q       cnt[7]      0.367       -0.224
cnt[3]       demo|clk_50M     DFFC     Q       cnt[3]      0.367       -0.095
cnt[5]       demo|clk_50M     DFFC     Q       cnt[5]      0.367       -0.095
cnt[2]       demo|clk_50M     DFFC     Q       cnt[2]      0.367       -0.028
cnt[9]       demo|clk_50M     DFFC     Q       cnt[9]      0.367       -0.014
cnt[10]      demo|clk_50M     DFFC     Q       cnt[10]     0.367       0.182 
=============================================================================


<a name=endingSlack16></a>Ending Points with Worst Slack</a>
******************************

             Starting                                             Required           
Instance     Reference        Type      Pin     Net               Time         Slack 
             Clock                                                                   
-------------------------------------------------------------------------------------
cnt[6]       demo|clk_50M     DFFC      D       cnt_3[6]          9.867        -0.568
cnt[11]      demo|clk_50M     DFFC      D       cnt_3[11]         9.867        -0.568
clk_spi      demo|clk_50M     DFFCE     CE      un1_cntlt24_i     9.867        1.275 
cnt[13]      demo|clk_50M     DFFC      D       cnt_3[13]         9.867        1.409 
cnt[14]      demo|clk_50M     DFFC      D       cnt_3[14]         9.867        1.409 
cnt[16]      demo|clk_50M     DFFC      D       cnt_3[16]         9.867        1.409 
cnt[18]      demo|clk_50M     DFFC      D       cnt_3[18]         9.867        1.409 
cnt[21]      demo|clk_50M     DFFC      D       cnt_3[21]         9.867        1.409 
cnt[12]      demo|clk_50M     DFFC      D       cnt_3[12]         9.867        1.815 
cnt[19]      demo|clk_50M     DFFC      D       cnt_3[19]         9.867        1.815 
=====================================================================================



<a name=worstPaths17></a>Worst Path Information</a>
<a href="C:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.srr:srsfC:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.srs:fp:40059:41553:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      10.435
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.568

    Number of logic level(s):                5
    Starting point:                          cnt[1] / Q
    Ending point:                            cnt[6] / D
    The start point is clocked by            demo|clk_50M [rising] on pin CLK
    The end   point is clocked by            demo|clk_50M [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[1]                 DFFC     Q        Out     0.367     0.367       -         
cnt[1]                 Net      -        -       1.021     -           2         
un1_cntlto10_N_2L1     LUT4     I1       In      -         1.388       -         
un1_cntlto10_N_2L1     LUT4     F        Out     1.099     2.487       -         
un1_cntlto10_N_2L1     Net      -        -       0.766     -           1         
un1_cntlto10           LUT4     I1       In      -         3.253       -         
un1_cntlto10           LUT4     F        Out     1.099     4.352       -         
un1_cntlt14            Net      -        -       1.021     -           3         
un1_cntlto17_0_0_1     LUT4     I1       In      -         5.373       -         
un1_cntlto17_0_0_1     LUT4     F        Out     1.099     6.472       -         
un1_cntlto17_0_0_1     Net      -        -       1.021     -           2         
un1_cntlto17_0_0       LUT4     I1       In      -         7.493       -         
un1_cntlto17_0_0       LUT4     F        Out     1.099     8.592       -         
un1_cntlt24            Net      -        -       1.021     -           2         
cnt_3[6]               LUT3     I2       In      -         9.613       -         
cnt_3[6]               LUT3     F        Out     0.822     10.435      -         
cnt_3[6]               Net      -        -       0.000     -           1         
cnt[6]                 DFFC     D        In      -         10.435      -         
=================================================================================
Total path delay (propagation time + setup) of 10.568 is 5.718(54.1%) logic and 4.850(45.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      10.435
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.568

    Number of logic level(s):                5
    Starting point:                          cnt[1] / Q
    Ending point:                            cnt[11] / D
    The start point is clocked by            demo|clk_50M [rising] on pin CLK
    The end   point is clocked by            demo|clk_50M [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[1]                 DFFC     Q        Out     0.367     0.367       -         
cnt[1]                 Net      -        -       1.021     -           2         
un1_cntlto10_N_2L1     LUT4     I1       In      -         1.388       -         
un1_cntlto10_N_2L1     LUT4     F        Out     1.099     2.487       -         
un1_cntlto10_N_2L1     Net      -        -       0.766     -           1         
un1_cntlto10           LUT4     I1       In      -         3.253       -         
un1_cntlto10           LUT4     F        Out     1.099     4.352       -         
un1_cntlt14            Net      -        -       1.021     -           3         
un1_cntlto17_0_0_1     LUT4     I1       In      -         5.373       -         
un1_cntlto17_0_0_1     LUT4     F        Out     1.099     6.472       -         
un1_cntlto17_0_0_1     Net      -        -       1.021     -           2         
un1_cntlto17_0_0       LUT4     I1       In      -         7.493       -         
un1_cntlto17_0_0       LUT4     F        Out     1.099     8.592       -         
un1_cntlt24            Net      -        -       1.021     -           2         
cnt_3[11]              LUT3     I2       In      -         9.613       -         
cnt_3[11]              LUT3     F        Out     0.822     10.435      -         
cnt_3[11]              Net      -        -       0.000     -           1         
cnt[11]                DFFC     D        In      -         10.435      -         
=================================================================================
Total path delay (propagation time + setup) of 10.568 is 5.718(54.1%) logic and 4.850(45.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      10.368
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.501

    Number of logic level(s):                5
    Starting point:                          cnt[0] / Q
    Ending point:                            cnt[6] / D
    The start point is clocked by            demo|clk_50M [rising] on pin CLK
    The end   point is clocked by            demo|clk_50M [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[0]                 DFFC     Q        Out     0.367     0.367       -         
cnt[0]                 Net      -        -       1.021     -           2         
un1_cntlto10_N_2L1     LUT4     I0       In      -         1.388       -         
un1_cntlto10_N_2L1     LUT4     F        Out     1.032     2.420       -         
un1_cntlto10_N_2L1     Net      -        -       0.766     -           1         
un1_cntlto10           LUT4     I1       In      -         3.186       -         
un1_cntlto10           LUT4     F        Out     1.099     4.285       -         
un1_cntlt14            Net      -        -       1.021     -           3         
un1_cntlto17_0_0_1     LUT4     I1       In      -         5.306       -         
un1_cntlto17_0_0_1     LUT4     F        Out     1.099     6.405       -         
un1_cntlto17_0_0_1     Net      -        -       1.021     -           2         
un1_cntlto17_0_0       LUT4     I1       In      -         7.426       -         
un1_cntlto17_0_0       LUT4     F        Out     1.099     8.525       -         
un1_cntlt24            Net      -        -       1.021     -           2         
cnt_3[6]               LUT3     I2       In      -         9.546       -         
cnt_3[6]               LUT3     F        Out     0.822     10.368      -         
cnt_3[6]               Net      -        -       0.000     -           1         
cnt[6]                 DFFC     D        In      -         10.368      -         
=================================================================================
Total path delay (propagation time + setup) of 10.501 is 5.651(53.8%) logic and 4.850(46.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      10.368
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.501

    Number of logic level(s):                5
    Starting point:                          cnt[0] / Q
    Ending point:                            cnt[11] / D
    The start point is clocked by            demo|clk_50M [rising] on pin CLK
    The end   point is clocked by            demo|clk_50M [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[0]                 DFFC     Q        Out     0.367     0.367       -         
cnt[0]                 Net      -        -       1.021     -           2         
un1_cntlto10_N_2L1     LUT4     I0       In      -         1.388       -         
un1_cntlto10_N_2L1     LUT4     F        Out     1.032     2.420       -         
un1_cntlto10_N_2L1     Net      -        -       0.766     -           1         
un1_cntlto10           LUT4     I1       In      -         3.186       -         
un1_cntlto10           LUT4     F        Out     1.099     4.285       -         
un1_cntlt14            Net      -        -       1.021     -           3         
un1_cntlto17_0_0_1     LUT4     I1       In      -         5.306       -         
un1_cntlto17_0_0_1     LUT4     F        Out     1.099     6.405       -         
un1_cntlto17_0_0_1     Net      -        -       1.021     -           2         
un1_cntlto17_0_0       LUT4     I1       In      -         7.426       -         
un1_cntlto17_0_0       LUT4     F        Out     1.099     8.525       -         
un1_cntlt24            Net      -        -       1.021     -           2         
cnt_3[11]              LUT3     I2       In      -         9.546       -         
cnt_3[11]              LUT3     F        Out     0.822     10.368      -         
cnt_3[11]              Net      -        -       0.000     -           1         
cnt[11]                DFFC     D        In      -         10.368      -         
=================================================================================
Total path delay (propagation time + setup) of 10.501 is 5.651(53.8%) logic and 4.850(46.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      10.158
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.291

    Number of logic level(s):                5
    Starting point:                          cnt[4] / Q
    Ending point:                            cnt[6] / D
    The start point is clocked by            demo|clk_50M [rising] on pin CLK
    The end   point is clocked by            demo|clk_50M [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[4]                 DFFC     Q        Out     0.367     0.367       -         
cnt[4]                 Net      -        -       1.021     -           2         
un1_cntlto10_N_2L1     LUT4     I2       In      -         1.388       -         
un1_cntlto10_N_2L1     LUT4     F        Out     0.822     2.210       -         
un1_cntlto10_N_2L1     Net      -        -       0.766     -           1         
un1_cntlto10           LUT4     I1       In      -         2.976       -         
un1_cntlto10           LUT4     F        Out     1.099     4.075       -         
un1_cntlt14            Net      -        -       1.021     -           3         
un1_cntlto17_0_0_1     LUT4     I1       In      -         5.096       -         
un1_cntlto17_0_0_1     LUT4     F        Out     1.099     6.195       -         
un1_cntlto17_0_0_1     Net      -        -       1.021     -           2         
un1_cntlto17_0_0       LUT4     I1       In      -         7.216       -         
un1_cntlto17_0_0       LUT4     F        Out     1.099     8.315       -         
un1_cntlt24            Net      -        -       1.021     -           2         
cnt_3[6]               LUT3     I2       In      -         9.336       -         
cnt_3[6]               LUT3     F        Out     0.822     10.158      -         
cnt_3[6]               Net      -        -       0.000     -           1         
cnt[6]                 DFFC     D        In      -         10.158      -         
=================================================================================
Total path delay (propagation time + setup) of 10.291 is 5.441(52.9%) logic and 4.850(47.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport18></a>Detailed Report for Clock: demo|clk_spi_derived_clock</a>
====================================



<a name=startingSlack19></a>Starting Points with Worst Slack</a>
********************************

                    Starting                                                                Arrival           
Instance            Reference                      Type      Pin     Net                    Time        Slack 
                    Clock                                                                                     
--------------------------------------------------------------------------------------------------------------
step_id[6]          demo|clk_spi_derived_clock     DFFC      Q       debug_step_id_c[6]     0.367       -3.887
step_id[5]          demo|clk_spi_derived_clock     DFFC      Q       debug_step_id_c[5]     0.367       -3.820
step_id[4]          demo|clk_spi_derived_clock     DFFC      Q       debug_step_id_c[4]     0.367       -1.891
step_id[2]          demo|clk_spi_derived_clock     DFFC      Q       debug_step_id_c[2]     0.367       -1.824
step_id[0]          demo|clk_spi_derived_clock     DFFC      Q       un1_step_id_1          0.367       0.339 
step_id[3]          demo|clk_spi_derived_clock     DFFC      Q       debug_step_id_c[3]     0.367       1.532 
step_id[1]          demo|clk_spi_derived_clock     DFFC      Q       debug_step_id_c[1]     0.367       1.646 
elapsed_time[1]     demo|clk_spi_derived_clock     DFFCE     Q       elapsed_time[1]        0.367       4.536 
elapsed_time[2]     demo|clk_spi_derived_clock     DFFCE     Q       elapsed_time[2]        0.367       4.593 
elapsed_time[3]     demo|clk_spi_derived_clock     DFFCE     Q       elapsed_time[3]        0.367       4.650 
==============================================================================================================


<a name=endingSlack20></a>Ending Points with Worst Slack</a>
******************************

                                                  Starting                                                                          Required           
Instance                                          Reference                      Type      Pin     Net                              Time         Slack 
                                                  Clock                                                                                                
-------------------------------------------------------------------------------------------------------------------------------------------------------
debug_waiting_for_step_time5_cry_27_0_RNI1VM2     demo|clk_spi_derived_clock     INV       I       debug_waiting_for_step_time5     10.000       -3.887
step_id[6]                                        demo|clk_spi_derived_clock     DFFC      D       un1_step_id_1_s_6_0_SUM          19.867       1.033 
step_id[5]                                        demo|clk_spi_derived_clock     DFFC      D       un1_step_id_1_cry_5_0_SUM        19.867       1.090 
step_id[4]                                        demo|clk_spi_derived_clock     DFFC      D       un1_step_id_1_cry_4_0_SUM        19.867       1.147 
step_id[3]                                        demo|clk_spi_derived_clock     DFFC      D       un1_step_id_1_cry_3_0_SUM        19.867       1.204 
step_id[2]                                        demo|clk_spi_derived_clock     DFFC      D       un1_step_id_1_cry_2_0_SUM        19.867       1.261 
step_id[1]                                        demo|clk_spi_derived_clock     DFFC      D       un1_step_id_1_cry_1_0_SUM        19.867       1.318 
step_id[0]                                        demo|clk_spi_derived_clock     DFFC      D       un1_step_id_1_cry_0_0_SUM        19.867       1.845 
spi0.debug_waiting_for_prescaler_RNO              demo|clk_spi_derived_clock     INV       I       un1__prescaler_cnt_1             10.000       4.904 
elapsed_time[0]                                   demo|clk_spi_derived_clock     DFFCE     CE      N_24                             19.867       4.948 
=======================================================================================================================================================



<a name=worstPaths21></a>Worst Path Information</a>
<a href="C:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.srr:srsfC:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.srs:fp:58571:69266:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      13.887
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -3.887

    Number of logic level(s):                30
    Starting point:                          step_id[6] / Q
    Ending point:                            debug_waiting_for_step_time5_cry_27_0_RNI1VM2 / I
    The start point is clocked by            demo|clk_spi_derived_clock [rising] on pin CLK
    The end   point is clocked by            System [rising]

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                              Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
step_id[6]                                        DFFC          Q        Out     0.367     0.367       -         
debug_step_id_c[6]                                Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m1                     LUT2          I1       In      -         1.388       -         
oled_rom_init.dout_1_47_0_.m1                     LUT2          F        Out     1.099     2.487       -         
N_65_mux                                          Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m16                    LUT2          I1       In      -         3.508       -         
oled_rom_init.dout_1_47_0_.m16                    LUT2          F        Out     1.099     4.607       -         
encoded_step[44]                                  Net           -        -       1.082     -           11        
oled_rom_init.dout_1_47_0_.m20                    LUT3          I0       In      -         5.689       -         
oled_rom_init.dout_1_47_0_.m20                    LUT3          F        Out     1.032     6.721       -         
m20                                               Net           -        -       1.021     -           3         
oled_rom_init.dout_1_47_0_.m49_am                 LUT3          I1       In      -         7.742       -         
oled_rom_init.dout_1_47_0_.m49_am                 LUT3          F        Out     1.099     8.841       -         
m49_am                                            Net           -        -       0.000     -           1         
oled_rom_init.dout_1_47_0_.m49                    MUX2_LUT5     I0       In      -         8.841       -         
oled_rom_init.dout_1_47_0_.m49                    MUX2_LUT5     O        Out     0.150     8.991       -         
encoded_step[19]                                  Net           -        -       1.021     -           1         
debug_waiting_for_step_time5_cry_3_0              ALU           I0       In      -         10.012      -         
debug_waiting_for_step_time5_cry_3_0              ALU           COUT     Out     0.958     10.970      -         
debug_waiting_for_step_time5_cry_3                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_4_0              ALU           CIN      In      -         10.970      -         
debug_waiting_for_step_time5_cry_4_0              ALU           COUT     Out     0.057     11.027      -         
debug_waiting_for_step_time5_cry_4                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_5_0              ALU           CIN      In      -         11.027      -         
debug_waiting_for_step_time5_cry_5_0              ALU           COUT     Out     0.057     11.084      -         
debug_waiting_for_step_time5_cry_5                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_6_0              ALU           CIN      In      -         11.084      -         
debug_waiting_for_step_time5_cry_6_0              ALU           COUT     Out     0.057     11.141      -         
debug_waiting_for_step_time5_cry_6                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_7_0              ALU           CIN      In      -         11.141      -         
debug_waiting_for_step_time5_cry_7_0              ALU           COUT     Out     0.057     11.198      -         
debug_waiting_for_step_time5_cry_7                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_8_0              ALU           CIN      In      -         11.198      -         
debug_waiting_for_step_time5_cry_8_0              ALU           COUT     Out     0.057     11.255      -         
debug_waiting_for_step_time5_cry_8                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_9_0              ALU           CIN      In      -         11.255      -         
debug_waiting_for_step_time5_cry_9_0              ALU           COUT     Out     0.057     11.312      -         
debug_waiting_for_step_time5_cry_9                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_10_0             ALU           CIN      In      -         11.312      -         
debug_waiting_for_step_time5_cry_10_0             ALU           COUT     Out     0.057     11.369      -         
debug_waiting_for_step_time5_cry_10               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_11_0             ALU           CIN      In      -         11.369      -         
debug_waiting_for_step_time5_cry_11_0             ALU           COUT     Out     0.057     11.426      -         
debug_waiting_for_step_time5_cry_11               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_12_0             ALU           CIN      In      -         11.426      -         
debug_waiting_for_step_time5_cry_12_0             ALU           COUT     Out     0.057     11.483      -         
debug_waiting_for_step_time5_cry_12               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_13_0             ALU           CIN      In      -         11.483      -         
debug_waiting_for_step_time5_cry_13_0             ALU           COUT     Out     0.057     11.540      -         
debug_waiting_for_step_time5_cry_13               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_14_0             ALU           CIN      In      -         11.540      -         
debug_waiting_for_step_time5_cry_14_0             ALU           COUT     Out     0.057     11.597      -         
debug_waiting_for_step_time5_cry_14               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_15_0             ALU           CIN      In      -         11.597      -         
debug_waiting_for_step_time5_cry_15_0             ALU           COUT     Out     0.057     11.654      -         
debug_waiting_for_step_time5_cry_15               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_16_0             ALU           CIN      In      -         11.654      -         
debug_waiting_for_step_time5_cry_16_0             ALU           COUT     Out     0.057     11.711      -         
debug_waiting_for_step_time5_cry_16               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_17_0             ALU           CIN      In      -         11.711      -         
debug_waiting_for_step_time5_cry_17_0             ALU           COUT     Out     0.057     11.768      -         
debug_waiting_for_step_time5_cry_17               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_18_0             ALU           CIN      In      -         11.768      -         
debug_waiting_for_step_time5_cry_18_0             ALU           COUT     Out     0.057     11.825      -         
debug_waiting_for_step_time5_cry_18               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_19_0             ALU           CIN      In      -         11.825      -         
debug_waiting_for_step_time5_cry_19_0             ALU           COUT     Out     0.057     11.882      -         
debug_waiting_for_step_time5_cry_19               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_20_0             ALU           CIN      In      -         11.882      -         
debug_waiting_for_step_time5_cry_20_0             ALU           COUT     Out     0.057     11.939      -         
debug_waiting_for_step_time5_cry_20               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_21_0             ALU           CIN      In      -         11.939      -         
debug_waiting_for_step_time5_cry_21_0             ALU           COUT     Out     0.057     11.996      -         
debug_waiting_for_step_time5_cry_21               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_22_0             ALU           CIN      In      -         11.996      -         
debug_waiting_for_step_time5_cry_22_0             ALU           COUT     Out     0.057     12.053      -         
debug_waiting_for_step_time5_cry_22               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_23_0             ALU           CIN      In      -         12.053      -         
debug_waiting_for_step_time5_cry_23_0             ALU           COUT     Out     0.057     12.110      -         
debug_waiting_for_step_time5_cry_23               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_24_0             ALU           CIN      In      -         12.110      -         
debug_waiting_for_step_time5_cry_24_0             ALU           COUT     Out     0.057     12.167      -         
debug_waiting_for_step_time5_cry_24               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_25_0             ALU           CIN      In      -         12.167      -         
debug_waiting_for_step_time5_cry_25_0             ALU           COUT     Out     0.057     12.224      -         
debug_waiting_for_step_time5_cry_25               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_26_0             ALU           CIN      In      -         12.224      -         
debug_waiting_for_step_time5_cry_26_0             ALU           COUT     Out     0.057     12.281      -         
debug_waiting_for_step_time5_cry_26               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_27_0             ALU           CIN      In      -         12.281      -         
debug_waiting_for_step_time5_cry_27_0             ALU           COUT     Out     0.057     12.338      -         
debug_waiting_for_step_time5                      Net           -        -       1.549     -           4         
debug_waiting_for_step_time5_cry_27_0_RNI1VM2     INV           I        In      -         13.887      -         
=================================================================================================================
Total path delay (propagation time + setup) of 13.887 is 7.172(51.6%) logic and 6.715(48.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      13.820
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.820

    Number of logic level(s):                30
    Starting point:                          step_id[5] / Q
    Ending point:                            debug_waiting_for_step_time5_cry_27_0_RNI1VM2 / I
    The start point is clocked by            demo|clk_spi_derived_clock [rising] on pin CLK
    The end   point is clocked by            System [rising]

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                              Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
step_id[5]                                        DFFC          Q        Out     0.367     0.367       -         
debug_step_id_c[5]                                Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m1                     LUT2          I0       In      -         1.388       -         
oled_rom_init.dout_1_47_0_.m1                     LUT2          F        Out     1.032     2.420       -         
N_65_mux                                          Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m16                    LUT2          I1       In      -         3.441       -         
oled_rom_init.dout_1_47_0_.m16                    LUT2          F        Out     1.099     4.540       -         
encoded_step[44]                                  Net           -        -       1.082     -           11        
oled_rom_init.dout_1_47_0_.m20                    LUT3          I0       In      -         5.622       -         
oled_rom_init.dout_1_47_0_.m20                    LUT3          F        Out     1.032     6.654       -         
m20                                               Net           -        -       1.021     -           3         
oled_rom_init.dout_1_47_0_.m49_am                 LUT3          I1       In      -         7.675       -         
oled_rom_init.dout_1_47_0_.m49_am                 LUT3          F        Out     1.099     8.774       -         
m49_am                                            Net           -        -       0.000     -           1         
oled_rom_init.dout_1_47_0_.m49                    MUX2_LUT5     I0       In      -         8.774       -         
oled_rom_init.dout_1_47_0_.m49                    MUX2_LUT5     O        Out     0.150     8.924       -         
encoded_step[19]                                  Net           -        -       1.021     -           1         
debug_waiting_for_step_time5_cry_3_0              ALU           I0       In      -         9.945       -         
debug_waiting_for_step_time5_cry_3_0              ALU           COUT     Out     0.958     10.903      -         
debug_waiting_for_step_time5_cry_3                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_4_0              ALU           CIN      In      -         10.903      -         
debug_waiting_for_step_time5_cry_4_0              ALU           COUT     Out     0.057     10.960      -         
debug_waiting_for_step_time5_cry_4                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_5_0              ALU           CIN      In      -         10.960      -         
debug_waiting_for_step_time5_cry_5_0              ALU           COUT     Out     0.057     11.017      -         
debug_waiting_for_step_time5_cry_5                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_6_0              ALU           CIN      In      -         11.017      -         
debug_waiting_for_step_time5_cry_6_0              ALU           COUT     Out     0.057     11.074      -         
debug_waiting_for_step_time5_cry_6                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_7_0              ALU           CIN      In      -         11.074      -         
debug_waiting_for_step_time5_cry_7_0              ALU           COUT     Out     0.057     11.131      -         
debug_waiting_for_step_time5_cry_7                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_8_0              ALU           CIN      In      -         11.131      -         
debug_waiting_for_step_time5_cry_8_0              ALU           COUT     Out     0.057     11.188      -         
debug_waiting_for_step_time5_cry_8                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_9_0              ALU           CIN      In      -         11.188      -         
debug_waiting_for_step_time5_cry_9_0              ALU           COUT     Out     0.057     11.245      -         
debug_waiting_for_step_time5_cry_9                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_10_0             ALU           CIN      In      -         11.245      -         
debug_waiting_for_step_time5_cry_10_0             ALU           COUT     Out     0.057     11.302      -         
debug_waiting_for_step_time5_cry_10               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_11_0             ALU           CIN      In      -         11.302      -         
debug_waiting_for_step_time5_cry_11_0             ALU           COUT     Out     0.057     11.359      -         
debug_waiting_for_step_time5_cry_11               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_12_0             ALU           CIN      In      -         11.359      -         
debug_waiting_for_step_time5_cry_12_0             ALU           COUT     Out     0.057     11.416      -         
debug_waiting_for_step_time5_cry_12               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_13_0             ALU           CIN      In      -         11.416      -         
debug_waiting_for_step_time5_cry_13_0             ALU           COUT     Out     0.057     11.473      -         
debug_waiting_for_step_time5_cry_13               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_14_0             ALU           CIN      In      -         11.473      -         
debug_waiting_for_step_time5_cry_14_0             ALU           COUT     Out     0.057     11.530      -         
debug_waiting_for_step_time5_cry_14               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_15_0             ALU           CIN      In      -         11.530      -         
debug_waiting_for_step_time5_cry_15_0             ALU           COUT     Out     0.057     11.587      -         
debug_waiting_for_step_time5_cry_15               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_16_0             ALU           CIN      In      -         11.587      -         
debug_waiting_for_step_time5_cry_16_0             ALU           COUT     Out     0.057     11.644      -         
debug_waiting_for_step_time5_cry_16               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_17_0             ALU           CIN      In      -         11.644      -         
debug_waiting_for_step_time5_cry_17_0             ALU           COUT     Out     0.057     11.701      -         
debug_waiting_for_step_time5_cry_17               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_18_0             ALU           CIN      In      -         11.701      -         
debug_waiting_for_step_time5_cry_18_0             ALU           COUT     Out     0.057     11.758      -         
debug_waiting_for_step_time5_cry_18               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_19_0             ALU           CIN      In      -         11.758      -         
debug_waiting_for_step_time5_cry_19_0             ALU           COUT     Out     0.057     11.815      -         
debug_waiting_for_step_time5_cry_19               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_20_0             ALU           CIN      In      -         11.815      -         
debug_waiting_for_step_time5_cry_20_0             ALU           COUT     Out     0.057     11.872      -         
debug_waiting_for_step_time5_cry_20               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_21_0             ALU           CIN      In      -         11.872      -         
debug_waiting_for_step_time5_cry_21_0             ALU           COUT     Out     0.057     11.929      -         
debug_waiting_for_step_time5_cry_21               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_22_0             ALU           CIN      In      -         11.929      -         
debug_waiting_for_step_time5_cry_22_0             ALU           COUT     Out     0.057     11.986      -         
debug_waiting_for_step_time5_cry_22               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_23_0             ALU           CIN      In      -         11.986      -         
debug_waiting_for_step_time5_cry_23_0             ALU           COUT     Out     0.057     12.043      -         
debug_waiting_for_step_time5_cry_23               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_24_0             ALU           CIN      In      -         12.043      -         
debug_waiting_for_step_time5_cry_24_0             ALU           COUT     Out     0.057     12.100      -         
debug_waiting_for_step_time5_cry_24               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_25_0             ALU           CIN      In      -         12.100      -         
debug_waiting_for_step_time5_cry_25_0             ALU           COUT     Out     0.057     12.157      -         
debug_waiting_for_step_time5_cry_25               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_26_0             ALU           CIN      In      -         12.157      -         
debug_waiting_for_step_time5_cry_26_0             ALU           COUT     Out     0.057     12.214      -         
debug_waiting_for_step_time5_cry_26               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_27_0             ALU           CIN      In      -         12.214      -         
debug_waiting_for_step_time5_cry_27_0             ALU           COUT     Out     0.057     12.271      -         
debug_waiting_for_step_time5                      Net           -        -       1.549     -           4         
debug_waiting_for_step_time5_cry_27_0_RNI1VM2     INV           I        In      -         13.820      -         
=================================================================================================================
Total path delay (propagation time + setup) of 13.820 is 7.105(51.4%) logic and 6.715(48.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      13.734
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.734

    Number of logic level(s):                31
    Starting point:                          step_id[6] / Q
    Ending point:                            debug_waiting_for_step_time5_cry_27_0_RNI1VM2 / I
    The start point is clocked by            demo|clk_spi_derived_clock [rising] on pin CLK
    The end   point is clocked by            System [rising]

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                              Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
step_id[6]                                        DFFC          Q        Out     0.367     0.367       -         
debug_step_id_c[6]                                Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m1                     LUT2          I1       In      -         1.388       -         
oled_rom_init.dout_1_47_0_.m1                     LUT2          F        Out     1.099     2.487       -         
N_65_mux                                          Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m9                     LUT3          I2       In      -         3.508       -         
oled_rom_init.dout_1_47_0_.m9                     LUT3          F        Out     0.822     4.330       -         
m9                                                Net           -        -       1.082     -           14        
oled_rom_init.dout_1_47_0_.m14                    LUT3          I1       In      -         5.412       -         
oled_rom_init.dout_1_47_0_.m14                    LUT3          F        Out     1.099     6.511       -         
m14                                               Net           -        -       1.021     -           4         
oled_rom_init.dout_1_47_0_.m45_am                 LUT3          I1       In      -         7.532       -         
oled_rom_init.dout_1_47_0_.m45_am                 LUT3          F        Out     1.099     8.631       -         
m45_am                                            Net           -        -       0.000     -           1         
oled_rom_init.dout_1_47_0_.m45                    MUX2_LUT5     I0       In      -         8.631       -         
oled_rom_init.dout_1_47_0_.m45                    MUX2_LUT5     O        Out     0.150     8.781       -         
encoded_step[18]                                  Net           -        -       1.021     -           1         
debug_waiting_for_step_time5_cry_2_0              ALU           I0       In      -         9.802       -         
debug_waiting_for_step_time5_cry_2_0              ALU           COUT     Out     0.958     10.760      -         
debug_waiting_for_step_time5_cry_2                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_3_0              ALU           CIN      In      -         10.760      -         
debug_waiting_for_step_time5_cry_3_0              ALU           COUT     Out     0.057     10.817      -         
debug_waiting_for_step_time5_cry_3                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_4_0              ALU           CIN      In      -         10.817      -         
debug_waiting_for_step_time5_cry_4_0              ALU           COUT     Out     0.057     10.874      -         
debug_waiting_for_step_time5_cry_4                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_5_0              ALU           CIN      In      -         10.874      -         
debug_waiting_for_step_time5_cry_5_0              ALU           COUT     Out     0.057     10.931      -         
debug_waiting_for_step_time5_cry_5                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_6_0              ALU           CIN      In      -         10.931      -         
debug_waiting_for_step_time5_cry_6_0              ALU           COUT     Out     0.057     10.988      -         
debug_waiting_for_step_time5_cry_6                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_7_0              ALU           CIN      In      -         10.988      -         
debug_waiting_for_step_time5_cry_7_0              ALU           COUT     Out     0.057     11.045      -         
debug_waiting_for_step_time5_cry_7                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_8_0              ALU           CIN      In      -         11.045      -         
debug_waiting_for_step_time5_cry_8_0              ALU           COUT     Out     0.057     11.102      -         
debug_waiting_for_step_time5_cry_8                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_9_0              ALU           CIN      In      -         11.102      -         
debug_waiting_for_step_time5_cry_9_0              ALU           COUT     Out     0.057     11.159      -         
debug_waiting_for_step_time5_cry_9                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_10_0             ALU           CIN      In      -         11.159      -         
debug_waiting_for_step_time5_cry_10_0             ALU           COUT     Out     0.057     11.216      -         
debug_waiting_for_step_time5_cry_10               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_11_0             ALU           CIN      In      -         11.216      -         
debug_waiting_for_step_time5_cry_11_0             ALU           COUT     Out     0.057     11.273      -         
debug_waiting_for_step_time5_cry_11               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_12_0             ALU           CIN      In      -         11.273      -         
debug_waiting_for_step_time5_cry_12_0             ALU           COUT     Out     0.057     11.330      -         
debug_waiting_for_step_time5_cry_12               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_13_0             ALU           CIN      In      -         11.330      -         
debug_waiting_for_step_time5_cry_13_0             ALU           COUT     Out     0.057     11.387      -         
debug_waiting_for_step_time5_cry_13               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_14_0             ALU           CIN      In      -         11.387      -         
debug_waiting_for_step_time5_cry_14_0             ALU           COUT     Out     0.057     11.444      -         
debug_waiting_for_step_time5_cry_14               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_15_0             ALU           CIN      In      -         11.444      -         
debug_waiting_for_step_time5_cry_15_0             ALU           COUT     Out     0.057     11.501      -         
debug_waiting_for_step_time5_cry_15               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_16_0             ALU           CIN      In      -         11.501      -         
debug_waiting_for_step_time5_cry_16_0             ALU           COUT     Out     0.057     11.558      -         
debug_waiting_for_step_time5_cry_16               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_17_0             ALU           CIN      In      -         11.558      -         
debug_waiting_for_step_time5_cry_17_0             ALU           COUT     Out     0.057     11.615      -         
debug_waiting_for_step_time5_cry_17               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_18_0             ALU           CIN      In      -         11.615      -         
debug_waiting_for_step_time5_cry_18_0             ALU           COUT     Out     0.057     11.672      -         
debug_waiting_for_step_time5_cry_18               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_19_0             ALU           CIN      In      -         11.672      -         
debug_waiting_for_step_time5_cry_19_0             ALU           COUT     Out     0.057     11.729      -         
debug_waiting_for_step_time5_cry_19               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_20_0             ALU           CIN      In      -         11.729      -         
debug_waiting_for_step_time5_cry_20_0             ALU           COUT     Out     0.057     11.786      -         
debug_waiting_for_step_time5_cry_20               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_21_0             ALU           CIN      In      -         11.786      -         
debug_waiting_for_step_time5_cry_21_0             ALU           COUT     Out     0.057     11.843      -         
debug_waiting_for_step_time5_cry_21               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_22_0             ALU           CIN      In      -         11.843      -         
debug_waiting_for_step_time5_cry_22_0             ALU           COUT     Out     0.057     11.900      -         
debug_waiting_for_step_time5_cry_22               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_23_0             ALU           CIN      In      -         11.900      -         
debug_waiting_for_step_time5_cry_23_0             ALU           COUT     Out     0.057     11.957      -         
debug_waiting_for_step_time5_cry_23               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_24_0             ALU           CIN      In      -         11.957      -         
debug_waiting_for_step_time5_cry_24_0             ALU           COUT     Out     0.057     12.014      -         
debug_waiting_for_step_time5_cry_24               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_25_0             ALU           CIN      In      -         12.014      -         
debug_waiting_for_step_time5_cry_25_0             ALU           COUT     Out     0.057     12.071      -         
debug_waiting_for_step_time5_cry_25               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_26_0             ALU           CIN      In      -         12.071      -         
debug_waiting_for_step_time5_cry_26_0             ALU           COUT     Out     0.057     12.128      -         
debug_waiting_for_step_time5_cry_26               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_27_0             ALU           CIN      In      -         12.128      -         
debug_waiting_for_step_time5_cry_27_0             ALU           COUT     Out     0.057     12.185      -         
debug_waiting_for_step_time5                      Net           -        -       1.549     -           4         
debug_waiting_for_step_time5_cry_27_0_RNI1VM2     INV           I        In      -         13.734      -         
=================================================================================================================
Total path delay (propagation time + setup) of 13.734 is 7.019(51.1%) logic and 6.715(48.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      13.677
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.677

    Number of logic level(s):                30
    Starting point:                          step_id[6] / Q
    Ending point:                            debug_waiting_for_step_time5_cry_27_0_RNI1VM2 / I
    The start point is clocked by            demo|clk_spi_derived_clock [rising] on pin CLK
    The end   point is clocked by            System [rising]

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                              Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
step_id[6]                                        DFFC          Q        Out     0.367     0.367       -         
debug_step_id_c[6]                                Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m1                     LUT2          I1       In      -         1.388       -         
oled_rom_init.dout_1_47_0_.m1                     LUT2          F        Out     1.099     2.487       -         
N_65_mux                                          Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m9                     LUT3          I2       In      -         3.508       -         
oled_rom_init.dout_1_47_0_.m9                     LUT3          F        Out     0.822     4.330       -         
m9                                                Net           -        -       1.082     -           14        
oled_rom_init.dout_1_47_0_.m20                    LUT3          I1       In      -         5.412       -         
oled_rom_init.dout_1_47_0_.m20                    LUT3          F        Out     1.099     6.511       -         
m20                                               Net           -        -       1.021     -           3         
oled_rom_init.dout_1_47_0_.m49_am                 LUT3          I1       In      -         7.532       -         
oled_rom_init.dout_1_47_0_.m49_am                 LUT3          F        Out     1.099     8.631       -         
m49_am                                            Net           -        -       0.000     -           1         
oled_rom_init.dout_1_47_0_.m49                    MUX2_LUT5     I0       In      -         8.631       -         
oled_rom_init.dout_1_47_0_.m49                    MUX2_LUT5     O        Out     0.150     8.781       -         
encoded_step[19]                                  Net           -        -       1.021     -           1         
debug_waiting_for_step_time5_cry_3_0              ALU           I0       In      -         9.802       -         
debug_waiting_for_step_time5_cry_3_0              ALU           COUT     Out     0.958     10.760      -         
debug_waiting_for_step_time5_cry_3                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_4_0              ALU           CIN      In      -         10.760      -         
debug_waiting_for_step_time5_cry_4_0              ALU           COUT     Out     0.057     10.817      -         
debug_waiting_for_step_time5_cry_4                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_5_0              ALU           CIN      In      -         10.817      -         
debug_waiting_for_step_time5_cry_5_0              ALU           COUT     Out     0.057     10.874      -         
debug_waiting_for_step_time5_cry_5                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_6_0              ALU           CIN      In      -         10.874      -         
debug_waiting_for_step_time5_cry_6_0              ALU           COUT     Out     0.057     10.931      -         
debug_waiting_for_step_time5_cry_6                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_7_0              ALU           CIN      In      -         10.931      -         
debug_waiting_for_step_time5_cry_7_0              ALU           COUT     Out     0.057     10.988      -         
debug_waiting_for_step_time5_cry_7                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_8_0              ALU           CIN      In      -         10.988      -         
debug_waiting_for_step_time5_cry_8_0              ALU           COUT     Out     0.057     11.045      -         
debug_waiting_for_step_time5_cry_8                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_9_0              ALU           CIN      In      -         11.045      -         
debug_waiting_for_step_time5_cry_9_0              ALU           COUT     Out     0.057     11.102      -         
debug_waiting_for_step_time5_cry_9                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_10_0             ALU           CIN      In      -         11.102      -         
debug_waiting_for_step_time5_cry_10_0             ALU           COUT     Out     0.057     11.159      -         
debug_waiting_for_step_time5_cry_10               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_11_0             ALU           CIN      In      -         11.159      -         
debug_waiting_for_step_time5_cry_11_0             ALU           COUT     Out     0.057     11.216      -         
debug_waiting_for_step_time5_cry_11               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_12_0             ALU           CIN      In      -         11.216      -         
debug_waiting_for_step_time5_cry_12_0             ALU           COUT     Out     0.057     11.273      -         
debug_waiting_for_step_time5_cry_12               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_13_0             ALU           CIN      In      -         11.273      -         
debug_waiting_for_step_time5_cry_13_0             ALU           COUT     Out     0.057     11.330      -         
debug_waiting_for_step_time5_cry_13               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_14_0             ALU           CIN      In      -         11.330      -         
debug_waiting_for_step_time5_cry_14_0             ALU           COUT     Out     0.057     11.387      -         
debug_waiting_for_step_time5_cry_14               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_15_0             ALU           CIN      In      -         11.387      -         
debug_waiting_for_step_time5_cry_15_0             ALU           COUT     Out     0.057     11.444      -         
debug_waiting_for_step_time5_cry_15               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_16_0             ALU           CIN      In      -         11.444      -         
debug_waiting_for_step_time5_cry_16_0             ALU           COUT     Out     0.057     11.501      -         
debug_waiting_for_step_time5_cry_16               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_17_0             ALU           CIN      In      -         11.501      -         
debug_waiting_for_step_time5_cry_17_0             ALU           COUT     Out     0.057     11.558      -         
debug_waiting_for_step_time5_cry_17               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_18_0             ALU           CIN      In      -         11.558      -         
debug_waiting_for_step_time5_cry_18_0             ALU           COUT     Out     0.057     11.615      -         
debug_waiting_for_step_time5_cry_18               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_19_0             ALU           CIN      In      -         11.615      -         
debug_waiting_for_step_time5_cry_19_0             ALU           COUT     Out     0.057     11.672      -         
debug_waiting_for_step_time5_cry_19               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_20_0             ALU           CIN      In      -         11.672      -         
debug_waiting_for_step_time5_cry_20_0             ALU           COUT     Out     0.057     11.729      -         
debug_waiting_for_step_time5_cry_20               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_21_0             ALU           CIN      In      -         11.729      -         
debug_waiting_for_step_time5_cry_21_0             ALU           COUT     Out     0.057     11.786      -         
debug_waiting_for_step_time5_cry_21               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_22_0             ALU           CIN      In      -         11.786      -         
debug_waiting_for_step_time5_cry_22_0             ALU           COUT     Out     0.057     11.843      -         
debug_waiting_for_step_time5_cry_22               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_23_0             ALU           CIN      In      -         11.843      -         
debug_waiting_for_step_time5_cry_23_0             ALU           COUT     Out     0.057     11.900      -         
debug_waiting_for_step_time5_cry_23               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_24_0             ALU           CIN      In      -         11.900      -         
debug_waiting_for_step_time5_cry_24_0             ALU           COUT     Out     0.057     11.957      -         
debug_waiting_for_step_time5_cry_24               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_25_0             ALU           CIN      In      -         11.957      -         
debug_waiting_for_step_time5_cry_25_0             ALU           COUT     Out     0.057     12.014      -         
debug_waiting_for_step_time5_cry_25               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_26_0             ALU           CIN      In      -         12.014      -         
debug_waiting_for_step_time5_cry_26_0             ALU           COUT     Out     0.057     12.071      -         
debug_waiting_for_step_time5_cry_26               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_27_0             ALU           CIN      In      -         12.071      -         
debug_waiting_for_step_time5_cry_27_0             ALU           COUT     Out     0.057     12.128      -         
debug_waiting_for_step_time5                      Net           -        -       1.549     -           4         
debug_waiting_for_step_time5_cry_27_0_RNI1VM2     INV           I        In      -         13.677      -         
=================================================================================================================
Total path delay (propagation time + setup) of 13.677 is 6.962(50.9%) logic and 6.715(49.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      13.667
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.667

    Number of logic level(s):                31
    Starting point:                          step_id[5] / Q
    Ending point:                            debug_waiting_for_step_time5_cry_27_0_RNI1VM2 / I
    The start point is clocked by            demo|clk_spi_derived_clock [rising] on pin CLK
    The end   point is clocked by            System [rising]

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                              Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
step_id[5]                                        DFFC          Q        Out     0.367     0.367       -         
debug_step_id_c[5]                                Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m1                     LUT2          I0       In      -         1.388       -         
oled_rom_init.dout_1_47_0_.m1                     LUT2          F        Out     1.032     2.420       -         
N_65_mux                                          Net           -        -       1.021     -           5         
oled_rom_init.dout_1_47_0_.m9                     LUT3          I2       In      -         3.441       -         
oled_rom_init.dout_1_47_0_.m9                     LUT3          F        Out     0.822     4.263       -         
m9                                                Net           -        -       1.082     -           14        
oled_rom_init.dout_1_47_0_.m14                    LUT3          I1       In      -         5.345       -         
oled_rom_init.dout_1_47_0_.m14                    LUT3          F        Out     1.099     6.444       -         
m14                                               Net           -        -       1.021     -           4         
oled_rom_init.dout_1_47_0_.m45_am                 LUT3          I1       In      -         7.465       -         
oled_rom_init.dout_1_47_0_.m45_am                 LUT3          F        Out     1.099     8.564       -         
m45_am                                            Net           -        -       0.000     -           1         
oled_rom_init.dout_1_47_0_.m45                    MUX2_LUT5     I0       In      -         8.564       -         
oled_rom_init.dout_1_47_0_.m45                    MUX2_LUT5     O        Out     0.150     8.714       -         
encoded_step[18]                                  Net           -        -       1.021     -           1         
debug_waiting_for_step_time5_cry_2_0              ALU           I0       In      -         9.735       -         
debug_waiting_for_step_time5_cry_2_0              ALU           COUT     Out     0.958     10.693      -         
debug_waiting_for_step_time5_cry_2                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_3_0              ALU           CIN      In      -         10.693      -         
debug_waiting_for_step_time5_cry_3_0              ALU           COUT     Out     0.057     10.750      -         
debug_waiting_for_step_time5_cry_3                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_4_0              ALU           CIN      In      -         10.750      -         
debug_waiting_for_step_time5_cry_4_0              ALU           COUT     Out     0.057     10.807      -         
debug_waiting_for_step_time5_cry_4                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_5_0              ALU           CIN      In      -         10.807      -         
debug_waiting_for_step_time5_cry_5_0              ALU           COUT     Out     0.057     10.864      -         
debug_waiting_for_step_time5_cry_5                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_6_0              ALU           CIN      In      -         10.864      -         
debug_waiting_for_step_time5_cry_6_0              ALU           COUT     Out     0.057     10.921      -         
debug_waiting_for_step_time5_cry_6                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_7_0              ALU           CIN      In      -         10.921      -         
debug_waiting_for_step_time5_cry_7_0              ALU           COUT     Out     0.057     10.978      -         
debug_waiting_for_step_time5_cry_7                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_8_0              ALU           CIN      In      -         10.978      -         
debug_waiting_for_step_time5_cry_8_0              ALU           COUT     Out     0.057     11.035      -         
debug_waiting_for_step_time5_cry_8                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_9_0              ALU           CIN      In      -         11.035      -         
debug_waiting_for_step_time5_cry_9_0              ALU           COUT     Out     0.057     11.092      -         
debug_waiting_for_step_time5_cry_9                Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_10_0             ALU           CIN      In      -         11.092      -         
debug_waiting_for_step_time5_cry_10_0             ALU           COUT     Out     0.057     11.149      -         
debug_waiting_for_step_time5_cry_10               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_11_0             ALU           CIN      In      -         11.149      -         
debug_waiting_for_step_time5_cry_11_0             ALU           COUT     Out     0.057     11.206      -         
debug_waiting_for_step_time5_cry_11               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_12_0             ALU           CIN      In      -         11.206      -         
debug_waiting_for_step_time5_cry_12_0             ALU           COUT     Out     0.057     11.263      -         
debug_waiting_for_step_time5_cry_12               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_13_0             ALU           CIN      In      -         11.263      -         
debug_waiting_for_step_time5_cry_13_0             ALU           COUT     Out     0.057     11.320      -         
debug_waiting_for_step_time5_cry_13               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_14_0             ALU           CIN      In      -         11.320      -         
debug_waiting_for_step_time5_cry_14_0             ALU           COUT     Out     0.057     11.377      -         
debug_waiting_for_step_time5_cry_14               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_15_0             ALU           CIN      In      -         11.377      -         
debug_waiting_for_step_time5_cry_15_0             ALU           COUT     Out     0.057     11.434      -         
debug_waiting_for_step_time5_cry_15               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_16_0             ALU           CIN      In      -         11.434      -         
debug_waiting_for_step_time5_cry_16_0             ALU           COUT     Out     0.057     11.491      -         
debug_waiting_for_step_time5_cry_16               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_17_0             ALU           CIN      In      -         11.491      -         
debug_waiting_for_step_time5_cry_17_0             ALU           COUT     Out     0.057     11.548      -         
debug_waiting_for_step_time5_cry_17               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_18_0             ALU           CIN      In      -         11.548      -         
debug_waiting_for_step_time5_cry_18_0             ALU           COUT     Out     0.057     11.605      -         
debug_waiting_for_step_time5_cry_18               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_19_0             ALU           CIN      In      -         11.605      -         
debug_waiting_for_step_time5_cry_19_0             ALU           COUT     Out     0.057     11.662      -         
debug_waiting_for_step_time5_cry_19               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_20_0             ALU           CIN      In      -         11.662      -         
debug_waiting_for_step_time5_cry_20_0             ALU           COUT     Out     0.057     11.719      -         
debug_waiting_for_step_time5_cry_20               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_21_0             ALU           CIN      In      -         11.719      -         
debug_waiting_for_step_time5_cry_21_0             ALU           COUT     Out     0.057     11.776      -         
debug_waiting_for_step_time5_cry_21               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_22_0             ALU           CIN      In      -         11.776      -         
debug_waiting_for_step_time5_cry_22_0             ALU           COUT     Out     0.057     11.833      -         
debug_waiting_for_step_time5_cry_22               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_23_0             ALU           CIN      In      -         11.833      -         
debug_waiting_for_step_time5_cry_23_0             ALU           COUT     Out     0.057     11.890      -         
debug_waiting_for_step_time5_cry_23               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_24_0             ALU           CIN      In      -         11.890      -         
debug_waiting_for_step_time5_cry_24_0             ALU           COUT     Out     0.057     11.947      -         
debug_waiting_for_step_time5_cry_24               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_25_0             ALU           CIN      In      -         11.947      -         
debug_waiting_for_step_time5_cry_25_0             ALU           COUT     Out     0.057     12.004      -         
debug_waiting_for_step_time5_cry_25               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_26_0             ALU           CIN      In      -         12.004      -         
debug_waiting_for_step_time5_cry_26_0             ALU           COUT     Out     0.057     12.061      -         
debug_waiting_for_step_time5_cry_26               Net           -        -       0.000     -           1         
debug_waiting_for_step_time5_cry_27_0             ALU           CIN      In      -         12.061      -         
debug_waiting_for_step_time5_cry_27_0             ALU           COUT     Out     0.057     12.118      -         
debug_waiting_for_step_time5                      Net           -        -       1.549     -           4         
debug_waiting_for_step_time5_cry_27_0_RNI1VM2     INV           I        In      -         13.667      -         
=================================================================================================================
Total path delay (propagation time + setup) of 13.667 is 6.952(50.9%) logic and 6.715(49.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport22></a>Detailed Report for Clock: demo|wr_spi_derived_clock[0]</a>
====================================



<a name=startingSlack23></a>Starting Points with Worst Slack</a>
********************************

                                Starting                                                                     Arrival          
Instance                        Reference                        Type     Pin     Net                        Time        Slack
                                Clock                                                                                         
------------------------------------------------------------------------------------------------------------------------------
spi0._tx_buffer_occupied[0]     demo|wr_spi_derived_clock[0]     DFFC     Q       _tx_buffer_occupied[0]     0.367       1.566
spi0._tx_buffer[7]              demo|wr_spi_derived_clock[0]     DFFC     Q       _tx_buffer[7]              0.367       7.380
spi0._tx_buffer[0]              demo|wr_spi_derived_clock[0]     DFFC     Q       debug_tx_buffer[0]         0.367       7.447
spi0._tx_buffer[1]              demo|wr_spi_derived_clock[0]     DFFC     Q       debug_tx_buffer[1]         0.367       7.447
spi0._tx_buffer[2]              demo|wr_spi_derived_clock[0]     DFFC     Q       debug_tx_buffer[2]         0.367       7.447
spi0._tx_buffer[4]              demo|wr_spi_derived_clock[0]     DFFC     Q       _tx_buffer[4]              0.367       7.657
spi0._tx_buffer[5]              demo|wr_spi_derived_clock[0]     DFFC     Q       _tx_buffer[5]              0.367       7.657
spi0._tx_buffer[6]              demo|wr_spi_derived_clock[0]     DFFC     Q       _tx_buffer[6]              0.367       7.657
==============================================================================================================================


<a name=endingSlack24></a>Ending Points with Worst Slack</a>
******************************

                          Starting                                                         Required          
Instance                  Reference                        Type      Pin     Net           Time         Slack
                          Clock                                                                              
-------------------------------------------------------------------------------------------------------------
spi0._sck[0]              demo|wr_spi_derived_clock[0]     DFFC      D       _sck_6[0]     9.867        1.566
spi0._state[0]            demo|wr_spi_derived_clock[0]     DFFCE     CE      N_30          9.867        1.566
spi0._sck[1]              demo|wr_spi_derived_clock[0]     DFFC      D       _sck_6[1]     9.867        1.633
spi0._sck[2]              demo|wr_spi_derived_clock[0]     DFFC      D       _sck_6[2]     9.867        1.633
spi0._sck[4]              demo|wr_spi_derived_clock[0]     DFFC      D       _sck_6[4]     9.867        1.633
spi0._shift_reg_tx[0]     demo|wr_spi_derived_clock[0]     DFFCE     CE      N_32          9.867        2.259
spi0._shift_reg_tx[1]     demo|wr_spi_derived_clock[0]     DFFCE     CE      N_32          9.867        2.259
spi0._shift_reg_tx[2]     demo|wr_spi_derived_clock[0]     DFFCE     CE      N_32          9.867        2.259
spi0._shift_reg_tx[3]     demo|wr_spi_derived_clock[0]     DFFCE     CE      N_32          9.867        2.259
spi0._shift_reg_tx[4]     demo|wr_spi_derived_clock[0]     DFFCE     CE      N_32          9.867        2.259
=============================================================================================================



<a name=worstPaths25></a>Worst Path Information</a>
<a href="C:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.srr:srsfC:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.srs:fp:123968:125468:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      8.301
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 1.566

    Number of logic level(s):                4
    Starting point:                          spi0._tx_buffer_occupied[0] / Q
    Ending point:                            spi0._sck[0] / D
    The start point is clocked by            demo|wr_spi_derived_clock[0] [rising] on pin CLK
    The end   point is clocked by            demo|clk_spi_derived_clock [rising] on pin CLK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                    Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
spi0._tx_buffer_occupied[0]             DFFC     Q        Out     0.367     0.367       -         
_tx_buffer_occupied[0]                  Net      -        -       1.021     -           1         
spi0._tx_buffer_occupied_RNIGB6Q[0]     LUT2     I0       In      -         1.388       -         
spi0._tx_buffer_occupied_RNIGB6Q[0]     LUT2     F        Out     1.032     2.420       -         
N_77_i                                  Net      -        -       1.082     -           16        
spi0.debug22_NE                         LUT4     I0       In      -         3.502       -         
spi0.debug22_NE                         LUT4     F        Out     1.032     4.534       -         
debug23                                 Net      -        -       1.021     -           8         
spi0._rx_buffer_1_sqmuxa_0_a3           LUT4     I3       In      -         5.555       -         
spi0._rx_buffer_1_sqmuxa_0_a3           LUT4     F        Out     0.626     6.181       -         
_rx_buffer_1_sqmuxa                     Net      -        -       1.021     -           9         
spi0._sck_6[0]                          LUT4     I1       In      -         7.202       -         
spi0._sck_6[0]                          LUT4     F        Out     1.099     8.301       -         
_sck_6[0]                               Net      -        -       0.000     -           1         
spi0._sck[0]                            DFFC     D        In      -         8.301       -         
==================================================================================================
Total path delay (propagation time + setup) of 8.434 is 4.289(50.9%) logic and 4.145(49.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport26></a>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack27></a>Starting Points with Worst Slack</a>
********************************

                                                  Starting                                                          Arrival          
Instance                                          Reference     Type     Pin     Net                                Time        Slack
                                                  Clock                                                                              
-------------------------------------------------------------------------------------------------------------------------------------
spi0._state_RNIIVQ7[0]                            System        INV      O       _state_i[0]                        0.000       8.846
spi0._tx_buffer_occupied_RNIGB6Q_0[0]             System        INV      O       N_77_i_i                           0.000       8.846
cnt_spi_RNO[0]                                    System        INV      O       cnt_spi_i[0]                       0.000       8.846
spi0.debug_waiting_for_prescaler_RNO              System        INV      O       N_279_i                            0.000       8.846
debug_waiting_for_step_time5_cry_27_0_RNI1VM2     System        INV      O       debug_waiting_for_step_time5_i     0.000       8.846
spi0.elapsed_time_0_sqmuxa_i_a2_RNITJ9A           System        INV      O       N_61_i                             0.000       8.846
un2_elapsed_time_s_0                              System        INV      O       un2_elapsed_time_s_0               0.000       8.846
=====================================================================================================================================


<a name=endingSlack28></a>Ending Points with Worst Slack</a>
******************************

                                     Starting                                                           Required          
Instance                             Reference     Type      Pin     Net                                Time         Slack
                                     Clock                                                                                
--------------------------------------------------------------------------------------------------------------------------
spi0._state[0]                       System        DFFCE     D       _state_i[0]                        9.867        8.846
spi0._tx_buffer_occupied[0]          System        DFFC      D       N_77_i_i                           9.867        8.846
cnt_spi[0]                           System        DFFC      D       cnt_spi_i[0]                       9.867        8.846
spi0.debug_waiting_for_prescaler     System        DFFCE     D       N_279_i                            9.867        8.846
debug_waiting_for_spi[0]             System        DFFCE     CE      debug_waiting_for_step_time5_i     9.867        8.846
spi0.debug_waiting_for_tx_data       System        DFFCE     CE      _state_i[0]                        9.867        8.846
spi0.debug_waiting_for_tx_data       System        DFFCE     D       N_77_i_i                           9.867        8.846
elapsed_time[0]                      System        DFFCE     D       un2_elapsed_time_s_0               9.867        8.846
internal_state_machine[0]            System        DFFCE     CE      debug_waiting_for_step_time5_i     9.867        8.846
internal_state_machine[0]            System        DFFCE     D       N_61_i                             9.867        8.846
==========================================================================================================================



<a name=worstPaths29></a>Worst Path Information</a>
<a href="C:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.srr:srsfC:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.srs:fp:130678:130942:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 8.846

    Number of logic level(s):                0
    Starting point:                          spi0._state_RNIIVQ7[0] / O
    Ending point:                            spi0._state[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            demo|clk_spi_derived_clock [rising] on pin CLK

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                       Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
spi0._state_RNIIVQ7[0]     INV       O        Out     0.000     0.000       -         
_state_i[0]                Net       -        -       1.021     -           2         
spi0._state[0]             DFFCE     D        In      -         1.021       -         
======================================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 197MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 197MB)

---------------------------------------
<a name=resourceUsage30></a>Resource Usage Report for demo </a>

Mapping to part: gw1n_4lqfp144-6
Cell usage:
ALU             95 uses
DFFC            60 uses
DFFCE           68 uses
DFFPE           2 uses
GSR             1 use
INV             9 uses
MUX2_LUT5       21 uses
MUX2_LUT6       4 uses
LUT2            44 uses
LUT3            70 uses
LUT4            51 uses

I/O ports: 22
I/O primitives: 22
IBUF           6 uses
OBUF           14 uses
TBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   130 of 3456 (3%)
Total load per clock:
   demo|clk_50M: 26
   demo|clk_spi_derived_clock: 95
   demo|wr_spi_derived_clock[0]: 9

@S |Mapping Summary:
Total  LUTs: 165 (3%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 40MB peak: 197MB)

Process took 0h:00m:05s realtime, 0h:00m:04s cputime
# Fri Oct 26 09:08:37 2018

###########################################################]

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